Exemplary embodiments relate to a nonvolatile memory device and a method of operating the same and, more particularly, to a nonvolatile memory device and a method of operating the same, which can be applied to an erase operation of a memory cell.
A flash memory device is a representative nonvolatile memory device and is divided into a NOR type and a NAND type. The NOR type flash memory device is chiefly used to store a small amount of information at high speed. The NAND type flash memory device is chiefly used to store a large amount of information. Furthermore, the flash memory device performs a read operation for data output, a program operation for data input, and an erase operation for data erasure. In particular, the program operation and the erase operation of the NAND type flash memory device are executed by means of Fowler-Nordheim (FN) tunneling of electrons which are generated in a tunnel insulating layer between the P-well well and the floating gate of a memory cell. That is, electrons are injected from the P-well to the floating gate of the memory cell via the tunnel insulating layer by means of FN tunneling, so that the program operation of the flash memory device is performed. In this program operation, electrons are injected into only the floating gates of selected ones of a plurality of memory cells included in a memory cell block. Furthermore, electrons within the floating gate of the memory cell are discharged toward the P-well by means of FN tunneling, so that the erase operation of the flash memory device is performed. In this erase operation, data stored in all the memory cells included in a selected one of a plurality of memory cell blocks is erased at the same time. That is, the erase operation is performed per memory cell block.
FIG. 1 is a circuit diagram of memory cells and pass gates for illustrating the erase operation of a known flash memory device.
Referring to FIG. 1, during the erase operation, a bias voltage Vb of 0 V is supplied to a global word line GWL, and a bulk voltage VBK1 of 20 V is supplied to the P-wells of memory cells CA1 to CAn and CB1 to CBn (n is an integer). The sources and drains of the memory cells CA1 to CAn and CB1 to CBn become a floating state. Furthermore, a block selection signal BKSEL1 of a voltage (Vcc) level is inputted to the gate of an NMOS transistor NM1 coupled between the local word line WL1 and the global word line GWL of a selected (that is, to be erased) memory cell block A. Furthermore, a bulk voltage VBK2 of 0 V is supplied to the substrate (not shown) of the NMOS transistor NM1. The NMOS transistor NM1 is turned on in response to the block selection signal BKSEL1 and configured to couple the local word line WL1 to the global word line GWL. Consequently, the voltage of the local word line WL1 becomes 0 V, and a voltage difference of 20 V is generated between each of the control gates (not shown) of the memory cells CA1 to CAn, coupled to the local word line WL1, and each of the P-wells of the memory cells CA1 to CAn. Accordingly, the electrons of the floating gates of the memory cells CA1 to CAn are discharged toward the P-wells, so that the erase operation of the memory cell block A is performed.
Meanwhile, a block selection signal BKSEL2 of 0 V is supplied to the gate of an NMOS transistor NM2 coupled between the local word line WL2 and the global word line GWL of an unselected (that is, not to be erased) memory cell block B. Furthermore, a bulk voltage VBK2 of 0 V is supplied to the substrate of the NMOS transistor NM2. The NMOS transistor NM2 is turned off in response to the block selection signal BKSEL2 and configured to separate the local word line WL2 from the global word line GWL. Consequently, the local word line WL2 becomes a floating state. Next, the bulk voltage VBK1 of 20 V supplied to the P-wells of the memory cells CB1 to CBn is drained out to the local word line WL2 owing to a capacitive coupling phenomenon, so that the voltage level of the local word line WL2 is boosted up to about 19 V. Accordingly, a fine voltage difference of about 1 V is generated between the local word line WL2 and the P-wells of the memory cells CB1 to CBn, and thus electrons are not discharged from the floating gates of the memory cells CB1 to CBn. Consequently, during the time for which the erase operation of the memory cell block A is performed, the erase operation of the memory cell block B is not performed.
Meanwhile, with an increase in the number of erase/program cycles, a fast program phenomenon in which a threshold voltage exceeds a target voltage during the program operation or a slow erase phenomenon in which a threshold voltage is not sufficiently lowered below a target voltage during the erase operation is generated. This phenomenon is described in more detail below with reference to FIG. 2.
FIG. 2 is a characteristic graph illustrating a slow erase characteristic and a fast program characteristic according to the number of erase operations in a known art.
Referring to FIG. 2, although a program or erase operation is performed under the same conditions, a threshold voltage gradually becomes higher than a target voltage with an increase in the number of erase cycles after the program or erase operation. This phenomenon becomes worse because the amount of electrons trapped in a tunnel insulating layer between the floating gate of a memory cell and a semiconductor substrate is increased with an increase in the number of program/erase cycles. This means that the program operation is quickly performed or the erase operation is slowly performed.
Meanwhile, in order to discharge electrons accumulated in the floating gate toward the substrate during the erase operation, a high voltage has to be supplied to the substrate. With an increase in the voltage difference between the word line and the bulk of the substrate, the fast program and slow erase phenomena become worse.
FIG. 3 is a characteristic graph illustrating a slow erase characteristic and a fast program characteristic according to the levels of an erase voltage in a known art.
From FIG. 3, it can be seen that if an erase operation is performed in a state in which the voltage difference between the word line and the bulk is high (that is, in a high potential erase state), the fast program phenomenon and the slow erase phenomenon become worse. It can also be seen that if an erase operation is performed in the state in which the voltage difference between the word line and the bulk is relatively low (that is, in a low potential erase state), the fast program phenomenon and the slow erase phenomenon are minimized.
In order to prevent the fast program phenomenon and the slow erase phenomenon, the erase operation has to be performed in a state in which the voltage difference between the word line and the bulk is reduced. In this case, however, the time that it takes to perform the erase operation time is lengthened, and the erase operation may not be normally performed. After the erase operation, an erase verification operation is performed. In the case where the erase operation is not normally performed, a corresponding block is treated as an invalid block and is not used. In this case, there are problems in that the number of available blocks is reduced and the data storage capacity is reduced.